Aspects of semiconductor manufacturing technology include nonvolatile memory devices such as a floating gate memory device or a metal insulator semiconductor (MIS) memory device constructed having two or more multilayered dielectric layers. The floating gate memory device embodies memory characteristics using a potential well and may be constructed in an electrically erasable programmable read only memory (EEPROM) tunnel oxide (ETOX) structure. The ETOX structure is a simple stack structure which is presently being the most widely applicable as an EEPROM, or a split gate structure having two transistors for each cell. On the other hand, MIS type memory device performs a memory function using a trap existing at a dielectric layer bulk, a dielectric layer/dielectric layer interface, and a dielectric layer/semiconductor interface. A metal/silicon oxide nitride oxide semiconductor (MONOS/SONOS) structure, which is being presently applicable as a flash EEPROM, is a representative example.
A flash memory device has a source connection layer that interconnects sources of respective unit cells to form a source line. In recent years, a source line, which is a dopant diffusion layer obtained through a self-aligned source (SAS) process to achieve high integration of the flash memory device, has been greatly applied as the source connection layer of the flash memory device.
As illustrated in example FIG. 1, a method of forming a source line includes a step of forming shallow trench isolation 120 in substrate 110 to define active region 130. As illustrated in example FIG. 2, a stack gate is then formed on and/or over active region 130 and shallow trench isolation 120 is filled in the field region with, e.g., an oxide film, and is then etched by reactive ion etching (RIE) using a photoresist mask to form trench T. As illustrated in example FIG. 3, ions are implanted in substrate 110 where trench T is formed by double ion implantations, i.e., a vertical ion implantation (Iv) and a tilt ion implantation (It), to form common source 140 having laterally extending surface portions 141 and 143 and vertical surface portion 142 connected to each other as illustrated in example FIG. 4.
As illustrated in example FIG. 4, damage due to the RIE is removed through chemical dry etching (CDE) before the oxidation of a sidewall (SW). Specifically, the portion stressed due to the ion implantation and oxide film etching (oxide RIE) is removed by the CDE process. However, high etching selectivity between the oxide film and the substrate is required, and therefore, high-priced equipment is required, and an additional process is also required. Also, a margin is reduced at a subsequent photo process due to high step difference between the substrate and the etched shallow trench isolation. A read failure may also occur when a photoresist (PR) residue is generated at a valley portion of the portion where the shallow trench isolation is etched. For example, when the PR residue is generated at the valley portion, an oxide etch block is generated. Consequently, a subsequent ion implantation of a recessed common source (RCS) is blocked, with the result that a source line is not connected, and therefore, a floating phenomenon may occur. Also, an active damage is caused, when the shallow trench isolation is etched, with the result that annealing of the sidewall (SW) is required. When curing is not appropriately performed, dislocation occurs, with the result that a word line (W/L) stress failure may occur.
For example, the active damage may be caused, at the time of performing the oxide etching, as follows. While the source line is being etched, damage is caused at the active region adjacent thereto due to stress. As a result, the W/L stress is caused, and therefore, a stress failure may occur. Also, a CDE process and a SW annealing step are additionally required due to the damage to a control gate and a floating gate at the time of etching the shallow trench isolation. When curing is not appropriately performed, a retention failure may occur. For example, side poly damage is caused only at the source region at the time of performing the oxide etching at the recessed common source (PCS), with the result that an oxide film grows thinner than a drain region when forming oxide by a subsequent SW oxidation. Consequently, a retention failure occurs. In order to remove this phenomenon, it is required to remove the region where the damage is caused using CDE equipment which cause little damage. As a result, an additional process is required. Furthermore, the removal of the damaged regions using the CDE is an additional etching process, with the result that sheet resistance Rs of the recessed common source (RCS) increases.